Sorry, forgot to update CRC. Linux sets register 0x41 to 0xa1, while the option ROM will set it to 0xf1 or 0x Therefore, I chose to set register df to cause the option ROM to quit without detecting drives. The original bytes were e8 xx xx , where e8 is the opcode for the CALL instruction, and the bit immediate operand is the relative branch target. Jan 20 , Why can it be?. I tried modifying the option ROM to also configure register 0x to this value, but had many problems booting.
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JMB36x/37x Sata Controller
I did have some issues with the card being seated properly in the PCIe slot. JMB38X Controller 1.
Jun 23 Aug 3 Linux sets register 40 bit 2 to enable the IDE port? Here is the link: The bytes that were changed here are x86 code that reads the PCI configuration register and does something with the value.
JMicron JMB363 Add-on Card AHCI mode
I have read through this page and start to comprehend the edits needed. Jul 26 That is just a waste of time.
Thus it seems like setting 0x41[7: Mar 25 Show posts by this member only Post 3. Aug 28 Trying to do that in the option ROM causes a several-minute hang during boot raod/ahci loading the option ROM again, seemingly waiting for a disk and giving upeven when a PATA disk is present.
If so, I would start with the first patched ROM the one that sets df[1: Fernando Show info Posts:. The original bytes were e8 xx xxwhere e8 is the opcode jm36x the CALL instruction, and the bit immediate operand is the relative branch target.
JMicron JMB36X SATA Controller Driver Driver – TechSpot
Therefore, I chose to set register df to cause the option ROM to quit without detecting drives. Jan 8 It is not a data table containing some form of initial register values.
Header Type ‘non-bridge’ single-func Vendor: And if I try other driver like Nvidia?
Modify to check LBA access boundary to avoid device error. Jmicron JMB36x Driver under win 8.
Email will not be published required. The last byte of the file is used as a checksum. Those three bytes used to be a function call to a function that would read a byte from the PCI configuration space register diand return the result in cl. Please enter a reason for warning.
Oct 13 The release jmiccron hints at the existence of a newer 1. Dec 17 This seems to put the controller in AHCI mode.
This post does not match the desired netiquette of the Forum. Any pointers would be appreciated.