Typically we would use a FIFO of or words, so you’d get interrupted every or words. How does chaining work? For example, if you’d like to bump the src address 4 bytes after each element transfer, you can set ‘BIDX to 4. After the first one completes, it triggers the next channel to start. The data transfer starts when a timer interrupt occurs. Takes region specific configuration information and a semaphore handle as argument Returns handle to newly created instance. How does linking work?
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Triggers the transfer to begin Transfer: How do you program this transfer?
[meta-ti] [PATCH] edma3-lld: add new recipe for edma3 low level driver
It cannot be synced to a peripheral event. Please note as of Wednesday, August 15th, this wiki has been set to read only. When I levsl this project I get a transfer complete interrupt, but nothing is transferred. Regions restrict access to the channels from the peripheral masters.
This is the “minimum” transfer size.
However, with API libraries available, why do it the hard way? A leve of these indexes can automatically perform “channel sorting” on incoming or outgoing data “free of charge” – with no time penalty. The LLD was built specifically for syncing to peripheral events. The transfer config describes the transfers to be executed when triggered.
Added by Steven Hill about 5 years ago I desperately need some help here. This page was last modified on 21 Marchat Navigation menu Personal tools Log in Request account. Well, that depends on what your elvel needs and the type of sync and indexing covered later….
It is assumed that if a particular channel number x is reserved for a particular master then the TCC x is also reserved for that same master. So, for example, if you want to write a block of memory from the DSP, and then DMA that memory to another location, then read it with the DSP, you must do the following: Views Read View source View history.
BCNT specifies the number of “elements” in a “frame” or “line”. The APIs are relatively easy to use and most are self explanatory. From Texas Instruments Wiki.
EDMA3 Keystone SoC Devices
Do you want to interrupt the CPU when the transfer is complete? Is it possible that you need to invalidate your cache prior to validating the transfer has completed?
How many items to move A, B, and C counts Addresses: Abstract It consists of three 3 libraries: Share buttons are a little bit lower. Published by Michael Barton Modified over 2 years ago. But I have no feeling for the overhead cycles required to set up and initiate the DMA. It is easy to set up and use if all you’re doing are memory to memory transfers.
McBSP tied to a codec. How does linking work?
Still too slow for what I want, so I have implemented ping-pong buffers on both sides of the transfer to deal with the latency problem. Source and destination addresses are fairly obvious. The EDMA3 also allows for ” linking ” and “chaining” capabilities.
EDMA sample test application http: Export results from on-chip to off-chip afterward.